VLIW Architecture
A VLIW processor executes wide instructions that bundle several independent operations chosen in advance by the compiler.
Moving Scheduling to Compile Time
A superscalar processor uses complex hardware to find independent instructions at run time. A very long instruction word (VLIW) processor takes the opposite approach: the compiler analyzes the program ahead of time and packs several independent operations into one wide instruction, and the hardware simply issues all of them to parallel units each cycle. The parallelism is decided at compile time, not by the machine.
Simpler Hardware, Smarter Compiler
Because the compiler guarantees the operations in a bundle are independent, the processor needs no dynamic dependency-checking, no out-of-order scheduling, and no register renaming. This makes the hardware simpler, smaller, and more power-efficient for a given issue width. The burden shifts entirely to the compiler, which must find and schedule the parallelism.
- One wide instruction holds several operations, one per functional unit
- No hardware dependency analysis or dynamic scheduling
- Compiler is responsible for correctness and parallelism
The Compiler's Challenge
Extracting enough parallelism to fill wide bundles is hard. Compilers use aggressive techniques like trace scheduling and software pipelining to overlap loop iterations and speculate across branches. When no independent operation is available for a slot, the compiler inserts a no-operation, so poorly scheduled code wastes issue slots and bloats code size.
Strengths and Limits
VLIW works best when parallelism is regular and predictable, as in digital signal processing and media codecs, where inner loops are well understood at compile time. It struggles with unpredictable, branchy code and with the fact that memory latency is not known statically. VLIW also ties the binary to a specific hardware width. These limits kept VLIW out of general-purpose CPUs, but its ideas live on in DSPs, some accelerators, and the explicitly parallel instruction sets of specialized processors.