Translation Lookaside Buffer
A translation lookaside buffer caches recent virtual-to-physical address translations so the processor avoids walking page tables on every access.
Virtual Memory Needs Translation
Programs use virtual addresses that must be translated to physical addresses on every memory access. The translation lives in page tables in memory, but walking those tables on each access would be ruinously slow. A translation lookaside buffer (TLB) is a small, fast cache of recently used translations, sitting on the critical path of every load and store.
A Specialized Cache
The TLB caches page-table entries: mappings from a virtual page number to a physical page frame, plus permission and status bits. Because a hit must be found in a single cycle among many entries, the TLB is often fully or highly associative, implemented with content-addressable memory that compares the incoming virtual page against all stored entries at once.
- Hit: translation found immediately, access proceeds
- Miss: a page-table walk fetches the mapping and fills the TLB
- Entries carry permission bits checked alongside translation
Misses and Page Walks
On a TLB miss, a page-table walk traverses the multi-level page table in memory to find the translation, then installs it in the TLB. The walk may be done by dedicated hardware or by software, depending on the architecture. If the page is not resident in memory at all, the walk raises a page fault, an exception handled by the operating system, which brings the page in and resumes the instruction.
Organization and Coherence
Real processors use multiple TLBs: separate instruction and data TLBs, and multiple levels much like the cache hierarchy. Support for multiple page sizes reduces pressure by mapping large regions with single entries. When the operating system changes a mapping, stale TLB entries must be invalidated (a TLB shootdown across cores in a multiprocessor), a subtle and performance-sensitive operation. The TLB's speed directly bounds how fast every memory reference can be.