Memory Controllers
A memory controller translates a processor's memory requests into the precise timed command sequences that DRAM chips require.
The Bridge to DRAM
Dynamic RAM is fast in bulk but has a rigid, stateful command protocol: rows must be opened before columns can be read, opened rows must eventually be closed, and charge must be periodically refreshed. A memory controller sits between the processor's caches and the DRAM chips, turning simple read and write requests into the correct sequence of activate, read, write, precharge, and refresh commands with exact timing.
Banks, Rows, and Columns
DRAM is organized into banks, each a grid of rows and columns. Reading requires first activating a row into a sense-amplifier buffer (the row buffer), then reading columns from it. Accessing another row in the same bank forces a precharge then a new activate, which is slow. The controller tracks the open row in every bank and schedules around these constraints.
- Row-buffer hit: target row already open, fast column access
- Row-buffer miss: precharge then activate before access
- Bank parallelism: overlap operations across independent banks
Scheduling and Reordering
A good controller reorders pending requests to exploit locality: it may serve several requests to an already-open row before closing it, and interleave across banks to hide latency. Common policies balance throughput (favoring row-buffer hits) against fairness (not starving requests to closed rows). It must also honor timing parameters and issue periodic refresh without disrupting service too much.
Timing and Reliability
The controller enforces DRAM timing constraints, the many minimum delays between commands, and manages features like error-correcting codes that detect and fix bit flips. In systems that must be dependable, such as the control and data-acquisition electronics around large scientific instruments, error-correcting memory guards long-running computations against single-bit upsets. Modern controllers also handle multiple channels and ranks to widen bandwidth.
Memory controllers are now integrated on the processor die, cutting the latency that an off-chip controller once added.