DRAM Cell

A DRAM cell stores a bit as charge on a tiny capacitor, achieving high density but requiring periodic refresh.

Structure

A dynamic RAM cell is just one transistor and one capacitor. The capacitor holds a charge that represents the bit, and the transistor connects the capacitor to a bit line when the word line is asserted. This minimal cell is why DRAM is far denser than SRAM.

Why it needs refresh

The stored charge leaks away through the transistor and the capacitor's own imperfections. Left alone, a cell loses its value in a few milliseconds. To prevent this the whole array is refreshed periodically: each cell is read and written back to restore full charge.

Destructive read

Reading a DRAM cell drains the capacitor through the bit line, destroying the stored value. A sense amplifier detects the small voltage change and immediately rewrites the bit. Every read is therefore followed by a restore.

Trade-offs

DRAM's one-transistor cell gives high density, so it is used for main memory where capacity matters. The cost is lower speed than SRAM and the overhead of refresh and restore cycles. It is volatile, losing data when power is removed.

Access structure

Cells are arranged in a grid addressed by row and column. Activating a row copies it into sense amplifiers, then columns are selected from there, which is why DRAM has separate row and column address phases.