Hardware Description Languages

Verilog and VHDL describe digital hardware as text, letting engineers specify behavior and structure that tools turn into circuits.

Describing Hardware, Not Programs

A hardware description language (HDL) looks like code but specifies circuits. The two dominant languages are Verilog (and its successor SystemVerilog) and VHDL. Unlike software, an HDL describes structures that all exist and operate concurrently: many gates and registers running in parallel, driven by clocks, not a single thread of sequential statements.

Combinational and Sequential

HDL code separates two kinds of logic. Combinational logic computes outputs purely from current inputs, described with continuous assignments or combinational always/process blocks. Sequential logic has memory, described with blocks sensitive to a clock edge that infer flip-flops. Getting this distinction right is the core skill: an accidental latch or a missing reset is a classic HDL bug.

// A synchronous counter with reset
always @(posedge clk) begin
  if (rst)
    count <= 4'b0000;
  else
    count <= count + 1'b1;
end

Simulation Versus Synthesis

An HDL description serves two masters. For simulation, the full language runs on a computer to verify behavior with testbenches before any hardware exists. For synthesis, only a restricted, synthesizable subset is used, because a tool must map it to real gates. Constructs like arbitrary delays or file I/O are fine for a testbench but meaningless in silicon.

• Blocking versus non-blocking assignment changes inferred behavior
• A synthesizable subset excludes timing and simulation-only constructs
• Testbenches exercise the design; assertions check properties automatically

Toward Higher Levels

SystemVerilog adds richer types, interfaces, and verification features. Beyond RTL, high-level synthesis lets engineers describe behavior in C-like languages and have a tool generate the register-transfer implementation, useful for exploring complex datapaths quickly. Whatever the entry point, the flow eventually produces the register-transfer description that logic synthesis consumes.