Clock and Power Gating
Clock gating stops the clock to idle logic to cut switching power; power gating cuts supply to idle blocks to remove leakage.
Two Sources of Power
A digital chip dissipates power in two ways. Dynamic power comes from charging and discharging capacitance every time a signal switches, and it scales with clock frequency and activity. Static (leakage) power flows even when nothing switches, because transistors are never perfectly off. Clock gating attacks the first; power gating attacks the second.
Clock Gating
The clock network is one of the busiest signals on a chip, and every flip-flop it reaches burns dynamic power on each edge even if the flop's data is not changing. Clock gating inserts a gate that stops the clock to a block when it is idle, so those flops stop toggling and their dynamic power drops toward zero. A special glitch-free integrated clock-gating cell is used so the clock is only ever cut cleanly between edges.
- Cuts dynamic power in idle regions
- Applied at fine grain (individual registers) or coarse grain (whole units)
- Must be glitch-free to avoid spurious clock pulses
Power Gating
Clock gating leaves the transistors powered, so leakage continues. Power gating goes further and disconnects a block from the supply through large header or footer switch transistors, driving its leakage nearly to zero. The cost is that the block loses its state and needs time to power back up, so state that must survive is saved to always-on retention registers first.
Trade-offs and Control
Power gating pays off only if a block stays idle long enough to recover the energy spent powering it down and back up, and to tolerate the wake-up latency. Power-management logic tracks activity and decides when to gate. Together with voltage and frequency scaling, these techniques form the backbone of low-power design in everything from phones to large accelerators, where energy per operation is a first-order constraint.