Metastability

Metastability is the unstable, undefined state a flip-flop can enter when its timing rules are violated, resolving only after an unpredictable delay.

What it is

A bistable element has two stable states and one unstable balance point between them. If a clock edge samples a signal that is changing, the flip-flop can be driven toward that balance point, hovering at an intermediate voltage that is neither a valid 0 nor 1. This is metastability.

Why it happens

Every flip-flop requires its input to be stable for a setup and hold window around the clock edge. When an input changes inside that window, the internal feedback loop may not have enough drive toward either stable state, so it lingers near the tipping point.

Resolution time

A metastable node does eventually resolve to a valid level, but the time it takes is unbounded in principle and grows exponentially unlikely with each added nanosecond. There is no way to guarantee resolution by a fixed deadline, only to make failure vanishingly rare.

Synchronizers

Crossing a signal between unrelated clock domains risks metastability. The standard defense is a synchronizer: two or more flip-flops in series give a metastable first stage time to settle before the second stage samples it, reducing the failure rate to negligible.

The takeaway

Metastability cannot be eliminated, only made improbable. This is why asynchronous inputs must always pass through synchronizers and why timing constraints are treated as hard rules in synchronous design.