SR Latch
The SR latch is the simplest memory element, holding one bit using two cross-coupled gates with set and reset inputs.
What it does
An SR latch stores a single bit. It has a set input S that forces the stored value to 1 and a reset input R that forces it to 0. When both inputs are inactive, the latch holds its last value. This holding behavior is the essence of memory.
Cross-coupled construction
The latch is built from two NOR gates, each feeding the other's input. The feedback loop lets the circuit remember: once a state is set, the outputs reinforce each other and stay put until an input changes them. A NAND version exists with active-low inputs.
The forbidden state
Asserting both S and R at once is not allowed in the basic latch. It drives both outputs to the same value, breaking the normal complementary relationship, and the final state is unpredictable when the inputs release together. Designers avoid this input combination.
Behavior table
| S | R | Q next |
|---|---|---|
| 0 | 0 | Q (hold) |
| 0 | 1 | 0 |
| 1 | 0 | 1 |
| 1 | 1 | invalid |
Toward better latches
Adding an enable input gives a gated SR latch that only responds while enabled. Replacing the input logic to eliminate the forbidden state leads to the D latch, which is far more common in practice.