Superscalar Processors
A superscalar processor issues and executes several instructions per cycle by having multiple parallel execution units.
More Than One Per Cycle
A scalar pipeline completes at most one instruction per cycle. A superscalar processor breaks that ceiling by fetching, decoding, and issuing several instructions each cycle to multiple execution units running in parallel. A four-wide machine can, in the best case, retire four instructions per cycle. This exploits instruction-level parallelism: independent instructions that can run at the same time.
What It Takes
Issuing multiple instructions per cycle demands wide, parallel hardware at every stage: fetch several instructions at once, decode them together, check all the dependencies among them, and route them to available units. The dependency-checking logic grows roughly with the square of the issue width, which is a major reason issue widths plateau.
- Multiple ALUs, load/store units, and floating-point units
- Multi-ported register files to feed all units at once
- Wide instruction fetch and decode
Finding Parallelism
A superscalar core may issue in order or out of order. Out-of-order superscalar designs combine wide issue with dynamic scheduling and register renaming to find parallelism the compiler could not, at the price of complex control logic. In-order superscalar designs are simpler and lean on the compiler to arrange independent instructions.
Limits
Real programs have limited instruction-level parallelism: dependencies, branches, and memory stalls cap how many instructions are truly independent at any moment. Doubling the issue width rarely doubles performance. This diminishing return, together with power constraints, pushed the industry toward multiple cores and hardware multithreading, which expose thread-level parallelism instead of squeezing ever more from a single stream.
VLIW is an alternative: it bundles independent operations at compile time into one wide instruction, moving the scheduling work from hardware to the compiler.