Place and Route
Place and route assigns each gate a physical location on the chip and draws the wires that connect them, meeting timing and space limits.
Giving Logic a Location
Logic synthesis produces a netlist: which cells exist and how they connect, but not where they sit. Place and route (P&R), the heart of the physical design flow, gives every cell a coordinate on the silicon and then draws the metal wires that carry every connection, all while respecting the manufacturing rules and the timing budget.
Placement
Placement decides where each standard cell goes. Cells that talk to each other frequently should sit close so their connecting wires are short and fast, but everything must fit without overlap and leave room for wiring. The tool balances wire length, timing, congestion, and power, typically in global and detailed phases. A poor placement makes routing impossible or timing hopeless, so placement dominates the final quality.
Clock Tree and Routing
Before signal routing, a clock tree is built to deliver the clock to every flip-flop with nearly equal delay, minimizing skew so all registers sample together. Then routing connects every net across the chip's metal layers, avoiding shorts, obeying spacing rules, and keeping critical paths short. Congested regions where too many wires want the same space must be relieved by adjusting placement.
- Global placement, then legalization and detailed placement
- Clock-tree synthesis to control skew
- Global then detailed routing across many metal layers
Closing the Loop
After routing, wire lengths and loads are known exactly, so real parasitic resistances and capacitances can be extracted and fed to static timing analysis. If timing or design rules fail, the tool performs engineering change orders: resizing cells, adding buffers, or rerouting to fix the offending paths. This iterate-until-clean loop is physical closure, and it is where much of a chip's development schedule is spent.