Instruction Set Architecture
An instruction set architecture is the contract between software and hardware, defining the instructions, registers, and behavior a processor exposes.
The Hardware-Software Contract
An instruction set architecture (ISA) is the abstract specification of what a processor does, as seen by software: the set of instructions, the registers, the memory model, the data types, and how interrupts and exceptions behave. It is a stable contract. Many different microarchitectures (actual chip implementations) can realize the same ISA, so old software runs on new hardware and vice versa.
RISC and CISC
Two philosophies shaped ISAs. CISC (complex instruction set) designs, exemplified by x86, offer many rich instructions, some performing multi-step operations, with variable-length encodings. RISC (reduced instruction set) designs, like ARM and RISC-V, favor a small set of simple, fixed-length instructions that are easy to pipeline and decode. Modern CISC processors internally translate their complex instructions into RISC-like micro-operations, blurring the once-sharp distinction.
- CISC: many complex, variable-length instructions
- RISC: few simple, fixed-length, pipeline-friendly instructions
- Load/store architecture: only explicit loads and stores touch memory
What an ISA Specifies
An ISA defines the operations (arithmetic, logic, memory access, control flow), the addressing modes for locating operands, the register set and its conventions, the data formats, and the privilege levels that separate user from operating-system code. It also fixes the encoding of instructions into bits. Crucially it says what happens, not how fast or by what circuitry, leaving those to the implementation.
Why It Endures
A stable ISA is enormously valuable because it decouples software investment from hardware evolution: decades of programs keep running as chips are redesigned underneath. This is why ISAs are conservative and extended carefully, adding features like SIMD or virtualization without breaking existing code. Open ISAs such as RISC-V let anyone build compatible hardware, which has broadened experimentation in processor design across research and industry.