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Digital Logic & Circuits

System Buses and AXI/AMBA

On-chip interconnect standards like ARM's AMBA and its AXI protocol define how processors, memory, and peripherals exchange data.

From Shared Bus to Interconnect

Early systems used a single shared bus that only one master could drive at a time. As chips integrated more masters and peripherals, that model became a bottleneck. Modern systems-on-chip use standardized interconnect protocols, of which ARM's AMBA family is the most widespread, to connect many initiators and targets efficiently.

The AMBA Family

Kronos motion — data assimilation

AMBA defines several protocols for different needs. APB (Advanced Peripheral Bus) is simple and low-power, for slow control registers. AHB (Advanced High-performance Bus) is a higher-bandwidth pipelined bus. AXI (Advanced eXtensible Interface) is the high-performance standard for connecting processors, caches, and memory controllers.

AXI Channels

AXI's key feature is five independent channels: separate channels for read address, read data, write address, write data, and write response. Because address and data are decoupled, a master can issue several outstanding requests before any complete, and responses can return in a different order via transaction IDs. This overlap is what gives AXI its throughput.

Handshake and Backpressure

Every AXI channel uses a simple valid/ready handshake: the source asserts valid when it has data, the destination asserts ready when it can accept, and transfer happens only when both are high on the same clock edge. This provides natural backpressure and lets fast and slow components interoperate without loss. The same handshake discipline appears throughout digital design because it composes cleanly and tolerates varying latencies.

On-chip networks (NoCs) extend these ideas to routed, packet-switched fabrics for chips with very many components.