Propagation Delay

Propagation delay is the time from an input change to the resulting output change; it sets the speed limit of a logic path.

Definition

Propagation delay is the interval between an input transition and the moment the output responds. It is measured between defined reference points, usually the fifty-percent voltage crossings of the input and output edges, and is never zero for real gates.

Rise and fall are not equal

A gate often has different delays for a low-to-high output than for a high-to-low output, because the pull-up and pull-down networks differ. Datasheets list both as tpLH and tpHL, and the effective delay depends on the direction of the transition.

What increases delay

• More gates in series: delays add along a path.
• Heavier load: driving a large fan-out or long wire slows the edge.
• Higher fan-in: gates with many inputs are intrinsically slower.
• Lower supply voltage and higher temperature generally slow switching.

Critical path

The critical path is the slowest input-to-output route through a block. Its total delay determines how soon the outputs are guaranteed valid, and in a clocked system it sets the shortest usable clock period. Speeding up a design means shortening this path.

Glitches

Because signals along different paths arrive at slightly different times, a combinational output may momentarily show a wrong value, a glitch or hazard, before settling. Sampling only after the worst-case delay, as clocked logic does, avoids acting on these transients.

Practical takeaway

Correct logic is necessary but not sufficient; it must also settle in time. Timing analysis sums gate and wire delays along every path to confirm the whole circuit meets its speed target with margin.