Propagation Delay

Propagation delay is the time a gate takes for a change at its input to appear at its output, setting the speed of digital logic.

What it is

No gate switches instantly. Propagation delay is the interval between an input change and the resulting output change, measured at defined voltage thresholds. It arises from the time needed to charge and discharge the capacitances of transistors and wires.

Rise and fall

The delay can differ for a rising output versus a falling one, since pull-up and pull-down transistors are not identical. Designers often quote both, or an average. Output loading matters too: driving more inputs or longer wires adds capacitance and lengthens the delay.

Critical path

In a block of combinational logic the total delay along a path is the sum of the gate delays it passes through. The slowest such path from input to output, or between flip-flops, is the critical path. It determines the maximum clock frequency, since the clock period must exceed it.

Glitches

Because different paths through a circuit have different delays, an output can briefly show a wrong value before settling, called a glitch or hazard. Glitches are harmless in purely combinational outputs sampled after settling, but can cause trouble if they reach edge-triggered or asynchronous inputs.

Reducing delay

Delay is reduced by using fewer levels of logic, faster gates, less loading, and structures like carry-lookahead that flatten deep chains. This is central to meeting timing constraints.