Logic Levels and CMOS
Logic levels map continuous voltages onto 0 and 1 with noise margins, and CMOS is the transistor style that realizes them efficiently.
From voltage to bits
Digital circuits run on continuous voltages but interpret them as two symbols. A range near the supply reads as logic 1, a range near ground reads as logic 0, and a forbidden band between them is treated as invalid. Fixed thresholds decide which is which.
Noise margins
A gate guarantees valid output levels, VOH for high and VOL for low, that are stricter than the input thresholds VIH and VIL it will accept. The gaps between them are noise margins: the amount of interference a signal can pick up and still be read correctly. Larger margins mean more robust logic.
How CMOS works
- A pull-up network of p-channel transistors connects the output to the supply.
- A pull-down network of n-channel transistors connects it to ground.
- The two networks are complementary, so exactly one conducts in a settled state.
- Because they are never both fully on at rest, static current is very low.
Why the pull-down inverts
The n-channel pull-down conducts when its input is high, pulling the output low. This natural inversion is why NAND and NOR come for free while AND and OR need an extra inverter stage.
Switching behavior
During a transition both networks conduct briefly, drawing a short current pulse and charging the load capacitance. This dynamic activity, not static leakage, dominates energy use in fast digital logic, and it grows with switching frequency and load.
Why CMOS won
Low static power, strong noise margins, full-swing outputs, and clean composability made CMOS the standard for digital integrated circuits, from single gates to the largest processors.