Syndrome-Extraction Circuit Design
How the entangling gates in a stabilizer measurement are ordered and scheduled determines whether errors stay local and the code keeps its distance.
More than measuring a parity
Measuring a stabilizer means entangling an ancilla with the data qubits the stabilizer touches, then reading the ancilla. The naive circuit is correct on paper but dangerous in practice: the order of the entangling gates, timing collisions, and idle periods all change how a single fault propagates. Good circuit design keeps every likely fault correctable.
Scheduling on a 2D grid
In the surface code each data qubit is shared by up to four checks, so its four CNOTs to neighboring ancillas must be scheduled in a fixed order across the whole lattice. A poor order can let one ancilla fault create a pair of data errors aligned along a logical operator, halving the effective distance. The standard N or Z shaped schedule avoids this by construction.
- Gate order controls how a single fault spreads into data errors.
- Idle qubits accumulate error and should be minimized.
- Hook errors, where an ancilla fault becomes a weight-two data error, must align harmlessly.
- The schedule must respect the hardware's connectivity and parallelism.
Two failure modes dominate. Hook errors are ancilla faults that turn into two-qubit data errors; the schedule is chosen so hooks lie perpendicular to the logical operator they could otherwise shorten. Idling errors accumulate on qubits waiting their turn, so schedules pack gates to keep every qubit busy and shorten the cycle.
Modern tooling treats the whole cycle as a spacetime circuit and searches over gate orders to maximize the circuit-level distance, the smallest number of physical faults that causes a logical error. This circuit-level view, rather than the idealized code distance, is what actually predicts hardware performance.