Cache Coherence
Cache coherence keeps every core's cached copy of shared data consistent, an invisible service with real performance consequences.
The problem
In a multi-core processor each core has private caches. If two cores cache the same memory location and one writes to it, the other's copy becomes stale. Cache coherence is the hardware protocol that ensures all cores observe a single, consistent value, so shared-memory programming behaves as expected.
How it works
Most systems use a snooping or directory-based protocol, commonly of the MESI family, which tracks each line's state as Modified, Exclusive, Shared, or Invalid. When a core writes a line, other copies are invalidated; when a core reads a line another has modified, the current value is supplied and states are updated. The programmer never issues these operations, but they generate coherence traffic on the interconnect.
MESI states
- Modified: this cache has the only, dirty copy
- Exclusive: this cache has the only, clean copy
- Shared: multiple caches hold clean copies
- Invalid: the copy is stale and must be refetched
Performance cost
Coherence is not free. A line repeatedly written by different cores bounces between them, each transfer a coherence miss. False sharing, distinct variables on one line, triggers this even when there is no true data dependence. Highly contended shared counters and locks are common victims; per-thread accumulation combined at the end avoids the traffic.
Scaling limits
Snooping traffic grows with core count, which is why very large shared-memory domains are hard to build. Beyond a node, systems abandon hardware coherence and use explicit message passing with MPI, trading programming convenience for scalability.