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HPC & Compute

Coalesced Memory Access

When the threads of a warp read contiguous addresses, the hardware serves them in one wide memory transaction instead of many.

The idea

GPU global memory is delivered in wide transactions, typically 32, 64, or 128 bytes at a time. When the 32 threads of a warp access consecutive, aligned addresses, the hardware coalesces their requests into the minimum number of transactions, so nearly every byte fetched is used. When threads access scattered addresses, each may trigger its own transaction, most of whose bytes are discarded, wasting the majority of the delivered bandwidth.

The layout rule

Kronos motion — cta read papers

The practical rule is that consecutive threads should touch consecutive elements. For a 2D array, this usually means threads indexed along the fast-varying dimension. The classic trap is a stride: if thread i reads element i*stride, each thread lands in a different transaction and effective bandwidth collapses by roughly the stride factor. The same computation over a transposed layout can differ in speed by an order of magnitude purely from coalescing.

Structure of arrays

Data layout choices flow directly from this rule. An array of structures (each particle's x, y, z, energy stored together) forces strided access when a warp reads only x. A structure of arrays (all x values contiguous, all y values contiguous) lets a warp read one field with perfect coalescing. GPU codes therefore often store particle and field data as separate arrays per component.

In practice

When a Hyperion field-update kernel stores mesh data structure-of-arrays, a warp updating the magnetic field component reads one contiguous stream, coalescing fully. The same kernel over an array-of-structures layout would stride across interleaved components and lose most of its memory bandwidth.