Latency and Jitter in Control Systems
Why bounded, predictable timing matters as much as raw speed in a real-time plasma control system.
Two timing quantities
Latency is the delay from a plasma event to the actuator response; jitter is the variation in that delay from cycle to cycle. Both degrade control, but jitter is often the more insidious: a loop can be designed around a known constant delay, but unpredictable variation eats stability margin the designer cannot plan for.
The stability cost of delay
A pure time delay adds phase lag that grows with frequency, subtracting phase margin and capping the bandwidth a loop can achieve. For a loop fighting an exponential instability like vertical motion, delay directly reduces the maximum growth rate it can stabilize. Every microsecond of latency shrinks the safe operating region.
Sources of latency
- Sensor sampling and analog-to-digital conversion
- Data transport over the control network
- Computation of the control law and state estimation
- Actuator command output and power-supply response
- Any queuing or scheduling in the software path
Why determinism beats average speed
A control cycle that is usually fast but occasionally slow is worse than one that is always moderately fast, because the loop must be designed for the worst case. This is why the fast layers run on real-time operating systems or bare-metal FPGAs, avoid dynamic memory and general-purpose schedulers, and are engineered for a bounded worst-case cycle time, not a good average.
Budgeting the loop
Each fast loop is given a timing budget - a maximum allowed latency and jitter - and every component in its path must fit inside it. The budget is verified by measurement, not assumed, and violations are treated as defects. Deterministic timing is a designed property of the whole chain, sensor to actuator, not a hope.