Peres Gate

A three-qubit reversible gate combining a Toffoli and a CNOT, a compact primitive for reversible arithmetic.

Definition

The Peres gate is a three-qubit reversible gate that applies a Toffoli followed by a CNOT in a single named block. On inputs (a, b, c) it outputs (a, a⊕b, c⊕ab). It is prized in reversible-logic design because it computes both a sum bit and a carry-related term with a low gate cost.

Truth behavior

The first output copies a; the second is a⊕b; the third is c⊕(a AND b). This is precisely the pair of functions a half-adder needs, which is why Peres gates are the standard cell in reversible adders.

Adder construction

A ripple-carry adder built from Peres gates uses one Peres gate per bit position to produce the sum and carry, then a mirrored network to uncompute ancillas. Because a Peres gate contains a Toffoli plus a CNOT, its quantum cost is lower than realizing those two gates separately after optimization.

def peres(a, b, c):
    out_a = a
    out_b = a ^ b
    out_c = c ^ (a & b)
    return out_a, out_b, out_c

Uses

Peres gates appear throughout quantum arithmetic circuits — adders, multipliers, and comparators — where minimizing Toffoli and CNOT counts directly improves the T-count of the final fault-tolerant circuit. They pair naturally with Fredkin and Margolus cells in reversible-logic synthesis. See Fredkin gate and Margolus gate.