Discrete-Time Control
Digital controllers act at sample instants, not continuously; discrete-time analysis captures the effects of sampling, hold, and computation delay.
Control at Sample Instants
A digital controller sees the world only at sampling instants and changes its output only at update instants. Between samples it is blind and its output is held constant. Discrete-time control theory analyzes systems in this sampled form, which behaves differently from the continuous case and must be modeled to guarantee stability and performance.
The Z-Domain
Just as continuous systems are analyzed with the Laplace transform in the s-domain, discrete systems use the Z-transform in the z-domain. A sampled system is stable if all its poles lie inside the unit circle of the z-plane, the discrete analog of the left-half s-plane. Continuous designs are mapped to discrete equivalents through methods such as the bilinear transform, taking care that stability and frequency response are preserved.
Effects of Sampling and Hold
- The zero-order hold adds an average delay of half a sample period
- Computation adds further delay from sample to output
- Sampling limits observable bandwidth to below the Nyquist frequency
- Too slow a rate degrades performance a continuous design assumed
Why a Stable Design Can Fail Digitally
A controller designed in continuous time and then implemented digitally can behave worse or even become unstable if the sample rate is too low or the computation delay is large. The added phase lag from the hold and delay reduces phase margin. This is why sample rate is a control-design parameter, not just an implementation detail, and why fast, low-jitter timing is worth the engineering effort.
Practical Guidance
Sample fast enough that the discretization effects are small, commonly many times the closed-loop bandwidth, and account explicitly for the computation delay by including it in the model. Verify stability in the discrete domain, not only the continuous approximation. Where the loop must be fast relative to what a sampled processor can guarantee, the design moves toward hardware, whose effective sample rate can be far higher and whose timing is deterministic.