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Quantum for Fusion

VQE Ansatze: UCCSD vs Hardware-Efficient

The choice of parameterized circuit trades physical motivation against hardware depth, and both families hit real limits for fusion materials.

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Two families of trial state

VQE lives or dies by its ansatz, the parameterized circuit that prepares |psi(theta)>. Two families dominate. The unitary coupled-cluster (UCCSD) ansatz is chemically motivated; hardware-efficient ansatze are shallow circuits built from whatever native gates a device offers.

text
# Unitary coupled cluster, singles + doubles (UCCSD):
|psi(theta)> = exp( T(theta) - T(theta)^dag ) |HF>
T = sum_{ia} t_ia a_a^dag a_i                       # singles
  + sum_{ijab} t_ijab a_a^dag a_b^dag a_i a_j       # doubles
# implemented via Trotterized exponentials of Pauli strings

# Hardware-efficient (layer l of rotations + entanglers):
|psi(theta)> = prod_l [ U_ent . (x)_q Ry(theta_{l,q}) ] |0...0>

The trade

AnsatzStrengthWeakness
UCCSDphysically grounded, systematicdeep circuits, many terms -> NISQ-infeasible
Hardware-efficientshallow, native gatesbarren plateaus, no physical guarantee
ADAPT-VQEgrows operator pool adaptivelymany measurements to pick operators

Barren plateaus

For expressive random ansatze the variance of the cost gradient shrinks exponentially with qubit number n, so the optimization landscape becomes flat and untrainable. This is a fundamental obstacle, not a tuning issue.

text
Var[ d<H>/d(theta_k) ]  ~  O( 2^{-n} )   (barren plateau)
# gradients vanish exponentially -> optimizer sees noise, not signal
# mitigations: shallow/structured ansatze, local cost functions,
#              good initialization -- none fully solve it

For Kronos first-wall work, UCCSD is the accuracy reference but too deep for current hardware, while hardware-efficient circuits are runnable but risk barren plateaus. This tension is exactly why we consider VQE a benchmark rather than a production method, and why tensor networks remain the strong classical competitor to beat.

Content reviewed August 2026 · design-and-simulation stage