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AI Architecture › L2 · Data Fabric
L2 · Data Fabric

The 60+ Port Analog Telemetry Pipeline

More than sixty analog telemetry ports carry raw plasma and machine state out of the vessel into the acquisition chain, sampled below the microsecond.

THE STACK · click to jumpL7Ecosystem & StrategyL6Experience & VisualizationL5Applications & CopilotsL4OrchestrationL3Twin Modeling & AIL2Data FabricL1Control PlaneL0Foundation▲tlmctl▼L2 · DATA FABRICTelemetry, validation, and the machine's memory.160+ Port Telemetrysensor bus2Signal Validationrange & sanity3Feature Engineeringderived signals4Time-Series Archivefull history5Feature Storetraining-ready6Vector DBembeddings for RAGMACHINE TIEIngests from diagnostics; serves the twin (L3) and copilots (L5).KRONOS FUSION ENERGYAI-NATIVE S.M.A.R.T. GENERATORDATA FABRICSHEET 04REV. 2026-08L2 · AI-NATIVE STACK
L2 · Data Fabric — its place in the stack (left, click any layer) and its internal components (right). Telemetry rises; control descends.

The port budget

Both machines expose 60+ analog telemetry ports. A port is a physical, calibrated path from a sensor inside or on the machine, through a cryo-rated vacuum feedthrough, into a conditioning front end and a synchronized digitizer. The count is dominated by distributed arrays: Mirnov coil sets, multi-chord interferometry and Thomson scattering, flux-loop rings, REBCO strain gauges bonded across the high-field magnet set, ECE radiometer channels, fast-ion trackers, and neutron-flux monitors.

Analog first, deliberately

Signals leave the machine as analog voltages or currents because the physics is analog and the fastest transients — a Mirnov spike that precedes a disruption, a plug-density collapse in the mirror — cannot wait for in-vessel digitization. Analog transport preserves bandwidth to the digitizer, where a single disciplined clock timestamps every channel. This keeps cross-channel phase intact, which is what equilibrium reconstruction and MHD mode analysis depend on.

Breeder versus burner port mix

From port to feature

Each port's stream is validated, spatially normalized, and folded into features. The pipeline is engineered so that adding or losing a port degrades gracefully: a graph model over the sensor topology can impute a dropped channel (see dead-sensor masking) rather than stall the loop. The port list, its calibrations, and its wiring are versioned in the schema registry so the fabric always knows exactly what is connected.

The pipeline is a design specification validated in simulation; the physical ports are engineered for the FOAK machine whose construction begins Q2 2027.

Content reviewed August 2026 · design-and-simulation stage