Quantum Annealing vs Gate-Model Optimization
Annealers and gate-model QAOA solve the same Ising problems by different routes; Kronos benchmarks both without assuming either wins.
Two hardware philosophies
Combinatorial problems mapped to Ising form can be attacked two ways. A quantum annealer physically evolves a system from an easy Hamiltonian to the problem Hamiltonian, hoping to stay near the ground state. Gate-model QAOA approximates that evolution with a shallow, tunable digital circuit.
# Adiabatic / annealing schedule s: 0 -> 1 over anneal time T
H(s) = (1 - s) H_B + s H_C
# adiabatic theorem: stay in ground state if
# T >> max_s || dH/ds || / gap(s)^2
# gap(s) = spectral gap; small gaps -> exponentially slow annealsHow they compare
| Aspect | Annealer | Gate-model QAOA |
|---|---|---|
| Model | analog adiabatic evolution | digital variational circuit |
| Qubit counts | larger (thousands) | smaller (tens-hundreds) |
| Connectivity | fixed graph, needs minor-embedding | gate-defined, flexible |
| Guarantee | adiabatic if gap large enough | none; depends on angle tuning |
| Failure mode | small-gap slowdown | barren plateaus, noise |
The shared limitation
Both are limited by the same physics: hard instances tend to have exponentially small spectral gaps, which slow annealers and flatten QAOA landscapes alike. Neither has shown consistent advantage over strong classical heuristics (simulated annealing, parallel tempering, specialized solvers) on realistic industrial instances.
For Kronos scheduling and layout problems we keep both on the bench and always run the classical baseline. Minor-embedding overhead on annealers and depth limits on QAOA both erode any theoretical edge at the sizes we actually face. The mapping recipe both consume is on the QUBO/Ising page, and the overall stance is the honest NISQ assessment.