FPGA Fabric Selection
Choosing the control-plane FPGA is a determinism and radiation problem: clocking, I/O, resources, and tolerance to the machine's neutron and EM environment.
What drives the choice
The control-plane FPGA is selected for guarantees, not peak throughput. What matters is deterministic clocking, high-bandwidth deterministic I/O for the diagnostics constellation, enough logic and DSP resources for the control math, and tolerance of the machine's radiation and electromagnetic environment. A part that is fast on average but hard to bound is the wrong part.
Selection axes
- Clocking: low-jitter PLLs and reliable clock distribution for nanosecond skew.
- I/O: many deterministic serial/parallel lanes for the state-vector ingress.
- Resources: DSP slices for fixed-point MAC trees, block RAM for pipelines.
- Environment: radiation tolerance and placement away from peak neutron flux.
- Toolchain: mature timing closure and static analysis for WCET evidence.
Radiation and placement
Both machines produce neutrons — the breeder 14 MeV D-T neutrons at 85.0 MW fusion power, the burner a 5.44% neutron fraction from D-3He. Single-event upsets in an FPGA's configuration or logic must be considered. Kronos places control fabric where shielding keeps flux manageable, and uses configuration scrubbing and error-corrected memory so upsets are detected and corrected before they affect a decision.
Timing closure as acceptance
A fabric choice is only validated when the control design closes timing on it with margin and the toolchain can produce a defensible WCET report. The same platform is targeted for both machines' fast loops, so investing in one hardened, well-characterized fabric pays across the fleet. Upset handling ties into redundancy for the highest-grade functions.