FPGA Bitstream Encryption and Authentication

Control-loop bitstreams are both encrypted and authenticated, so an attacker can neither read the design nor load a modified one onto a Kronos control FPGA.

Two distinct guarantees

Bitstream security needs two separable properties. Encryption (confidentiality) stops an adversary from reverse-engineering the control design or extracting embedded secrets by reading flash or sniffing the configuration bus. Authentication (integrity) stops an adversary from loading a bitstream Kronos did not produce. Encryption alone is not enough: without an authentication tag, a malleable ciphertext can be altered. Kronos requires authenticated encryption on every configuration load.

Order of operations

The device authenticates before it decrypts and configures - a fail-closed order. If the authentication tag over the encrypted bitstream does not verify against the device's provisioned key, configuration is refused and the node halts, feeding the same fail-closed path as secure boot.

# Load path: verify then decrypt (authenticated encryption, e.g. AES-GCM)
def load_bitstream(blob):
    hdr, ct, tag = parse(blob)
    if not aead_verify(ct, tag, key=device_key, aad=hdr):
        halt('bitstream auth failed')     # refuse before decrypt
    plain = aead_decrypt(ct, key=device_key)
    if hdr.design_id not in policy.allowed_designs:
        halt('unexpected design id')
    configure_fabric(plain)

Key handling

• Bitstream keys are provisioned into device key stores and never exit the device; see secrets and key management.
• Each device (or small batch) has a distinct key so one extracted key does not compromise the fleet.
• Rollback of a bitstream to an older, signed-but-vulnerable version is blocked by a monotonic version field checked at load and re-checked in attestation.

Design status

Authenticated-encryption load logic and version-monotonicity checks are implemented on development boards and modeled in the twin. Per-device key provisioning and the tamper-resistant key store are part of FOAK hardware manufacturing; no production reactor FPGA is yet fielded.