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AI Architecture › L1 · Control Plane
L1 · Control Plane

Edge FPGA Microsecond-Deterministic Actuation

Field-programmable gate arrays at the machine edge execute control logic in fixed clock cycles, giving cycle-exact, jitter-free actuation for both machines.

THE STACK · click to jumpL7Ecosystem & StrategyL6Experience & VisualizationL5Applications & CopilotsL4OrchestrationL3Twin Modeling & AIL2Data FabricL1Control PlaneL0Foundation▲tlmctl▼L1 · CONTROL PLANEHard real-time actuation and the autonomous failsafe.1Edge FPGAµs-determinism2Real-Time Actuationcoils · heating · fuel3Hardware Failsafeautonomous trip4Sync Gatephase-locked timing5Signal I/OADC / DAC6Watchdogliveness & interlocksMACHINE TIEDrives magnets, ice-piston, and gas puff on the sub-10 µs loop.KRONOS FUSION ENERGYAI-NATIVE S.M.A.R.T. GENERATORCONTROL PLANESHEET 03REV. 2026-08L1 · AI-NATIVE STACK
L1 · Control Plane — its place in the stack (left, click any layer) and its internal components (right). Telemetry rises; control descends.

Why FPGAs at the edge

A general-purpose CPU running an operating system cannot promise when an instruction retires; caches, interrupts, and schedulers introduce variance. Kronos places the fastest control and all protection logic on FPGA fabric physically adjacent to the machine, where a computation compiled to gates executes in a known, fixed number of clock cycles every time.

Cycle-exact execution

At a fabric clock of, say, 200 MHz (5 ns/cycle), a pipeline of depth N completes in exactly N·5 ns regardless of input values. There is no instruction fetch, no branch misprediction, no cache miss. Latency equals pipeline depth times clock period, plus fixed I/O, which is why the 10 µs boundary is achievable with margin.

What runs in fabric

Fixed-point discipline

Fabric control math is implemented in fixed-point arithmetic with statically analyzed word growth, so numerical range and rounding are known at synthesis time. Where a gain matrix K multiplies a state vector x to form an actuation u = -Kx, the multiply-accumulate tree is fully unrolled and pipelined; the result is available every clock with deterministic quantization error bounded at design time.

Reprogrammability matters: the same board can host the breeder's shape controller or the burner's plug controller by loading a different bitstream. This lets Kronos share a hardened control-plane platform across both machines while keeping each loop specialized. Retraining and model updates happen offline at L0; the validated bitstream is the only thing that ever changes on the edge.

Content reviewed August 2026 · design-and-simulation stage