Cycle-Accurate FPGA Reflex Pipeline

The fastest loops run as fixed-depth FPGA pipelines where latency is an exact cycle count, not a statistic, making the reflex tier certifiable by construction.

Latency as arithmetic

On a general CPU, latency is a distribution shaped by caches, branch prediction, and the scheduler. On the FPGA reflex fabric, latency is arithmetic: a pipeline of fixed depth clocked at a fixed frequency produces a result exactly N cycles after its input, every time. This is what makes the fast path's WCET exact rather than estimated.

# a fixed-depth reflex pipeline: validate -> filter -> law -> clamp -> gate
STAGE_CYCLES = {'validate':3, 'filter':5, 'law':4, 'clamp':2, 'gate':1}
def pipeline_latency_ns(clk_hz):
    depth = sum(STAGE_CYCLES.values())      # 15 cycles, always
    return depth / clk_hz * 1e9

print(round(pipeline_latency_ns(250e6),1)) # 60.0 ns, deterministic
# throughput is one result per cycle once the pipeline is full

Design constraints that keep it exact

• No data-dependent branching in the datapath; use predicated logic.
• Fixed-tap filters and lookup tables, so every path through the logic has equal depth.
• No off-chip memory on the fast path; state lives in on-chip registers/BRAM.
• Registered I/O with the same clock domain to avoid metastability on the boundary.

Because throughput is one sample per clock once the pipeline is primed, the fabric can service many channels concurrently without adding latency — each channel is a parallel lane, not a queued job. This is why the reflex tier can watch the full magnetics and quench-sensing constellation without falling behind.

Parallel lanes also give the reflex tier its diversity of observation without added latency: many channels of magnetics, quench voltage, and coil strain are processed every cycle without any of them queuing behind the others. That constant, complete view is what lets voting and cross-consistency checks run inside the same tick as the control law, so a bad channel is caught in the cycle it goes bad rather than after a scan delay. Determinism and breadth of observation are the same property here.

CPUs and GPUs are not banned from Kronos — they run supervision, the twin, and offline training — but they are excluded from the certified fast path precisely because their timing is statistical. See reflex and supervisory tier separation.