Clock Distribution and Synchronization
A single low-jitter time reference is fanned out across the control plane so every FPGA, driver, and diagnostic shares one deterministic clock.
One clock, everywhere
Determinism across a distributed system requires a common notion of time. Kronos distributes a single low-jitter master clock and a synchronized time-of-day to every L1 node — FPGA controllers, actuator drivers, and the deterministic front end. Shared time is what makes synchronized gates, time-triggered links, and correlated diagnostics possible.
Fan-out and skew
The reference is fanned out through matched-length paths and clock buffers so that phase skew between nodes stays in the nanosecond range. Skew is budgeted like latency: every node's clock arrival is characterized, and the worst-case skew feeds the timing and jitter budgets of every cross-node operation.
Time-triggered operation
- Sampling instants aligned across diagnostics for coherent state vectors.
- Communication slots scheduled, not contended, on the deterministic fabric.
- Actuation gates released on shared clock edges.
- Event timestamps consistent across the L2 archive for later correlation.
Aligned sampling matters for physics: the breeder's Grad-Shafranov reconstruction is only valid if Mirnov coils, flux loops, and interferometry are sampled at the same instant; the burner's ambipolar-potential estimate needs its inputs time-coherent. A shared clock guarantees that the state vector is a snapshot, not a smear.
Holdover and integrity
If the master reference is disturbed, nodes hold over on local oscillators with characterized drift, and the system flags degraded synchronization. Loss of clock integrity is itself an interlock condition: coordinated actuation that depends on tight skew is inhibited until synchronization is restored, defaulting to the safe behavior consistent with the rest of L1.